The present embodiments relate to digital video systems and are more specifically directed to video decoders.
Modern high-performance video displays, including plasma and liquid-crystal displays (“LCD”), are adapted to receiving digital signals corresponding to the information to be displayed. These digital signals indicate the intensity, typically by component, to be displayed by each picture element (“pixel”) of the display. For example, modem “component” video signals may include a component value for each of the pixel attributes of luma (“Y”), chroma-blue (“Pb”), and chroma-red (“Pr”), where variants of this format also exist (e.g., YUV, YCbCr, and YIQ). As a result, modem high resolution displays, having many pixels in each dimension and with each pixel responsive to as much as a twenty-four bit digital signal, are able to render high fidelity images at real time data rates. Component signals also may be provided in other manners, with a simple approach being RGB, which consists of three signals, red (R), green (G), and blue (B), typically provided by three respective wires.
As known in the art, video inputs are communicated and processed in a wide variety of formats. Broadcast television signals are still communicated in the analog domain, and these analog signals are communicated according to different standards around the world. In addition, video signals from various sources are now also available as inputs for display on digital displays. These other sources include cable and satellite digital video transmissions, video cameras, and video playback devices such as DVD players and video cassette recorders. In any case, these signals may be in a component form of RGB signals or, alternatively, they may be in the form of “composite” video signals, sometimes referred to as CVBS. Various standards also exist in connection with these signals, such as for conventional video signals with standards including the well-known NTSC (National Television Systems Committee), PAL, and SECAM composite video signal standards, and in Europe there is SCART (Syndicat des Constructeurs d'Appareils Radiorécepteurs et Téléviseurs), which combines RGB and CVBS.
Video decoder functions are now commonly used in many high-performance digital display and television systems for receiving video signals from the above-described sources and converting the video signals into a digital form for display. For example, a so-called “set-top box” for receiving cable or satellite digital video transmissions and for driving a digital video display typically includes a video decoder function. Modern set-top boxes also often have auxiliary inputs for receiving video signals from other sources, from which the video decoder in the set-top box generates the digital video output signals. Other systems that include a video decoder function include video decoder cards for personal computers, personal video recorders (PVRs) for digitally recording broadcast, cable, or satellite transmissions for later viewing, digital video projectors, digital VCRs and DVD recorders, video or home theater receivers, and indeed digital television sets including HD television sets and computer displays that are themselves (i.e., without an external set-top box) capable of digitally displaying video output from conventional analog input signals.
The video decoder function in SCART systems has been implemented in the prior art using four different analog-to-digital converters (“ADCs”), where that number of ADCs corresponds to the four signals to be processed. Specifically, to support SCART, four ADCs have been used, with one for the CVBS signal, and three for the respective R, G, and B signals. To illustrate this aspect and for sake of contrast to the preferred embodiments described later, FIG. 1 illustrates a timing diagram of the output of each of these four ADCs, where the first row illustrates the digital output of the ADC receiving an analog input composite signal, thereby showing digital samples C0, C1, . . . C6, while the second through fourth rows illustrate the output of a respective ADC for each of the R, G, and B signals, thereby indicating the digital samples R0, R1, . . . R6 for the analog R signal input, G0, G1, . . . G6 for the analog G signal input, and B0, B1, . . . B6 for the analog B signal input Note also that the illustrated digital signals, per the prior art, are provided at a 2× over-sampling rate, that is, they are sampled at twice the frequency of the analog input signals.
The video decoder function for component signal support has required three different ADCs in the prior art, where that number of ADCs corresponds to the three signals to be processed, as forms of R, G, and B. For example, to support the YPbPr format, three ADCs have been used, with one for each of the respective Y, Pb, and Pr signals. To illustrate this aspect and for sake of contrast to the preferred embodiments described later, FIG. 2 illustrates a timing diagram of the output of each of these three ADCs, where the first row illustrates the digital output of the ADC receiving the Y component signal, thereby showing digital samples Y0, Y1, . . . Y9, while the second row illustrates the digital output of the ADC receiving the Pb component signal, thereby showing digital samples Pb0, Pb1, . . . Pb9, and the third row illustrates the digital output of the ADC receiving the Pr component signal, thereby showing digital samples Pr0, Pr1, . . . Pr9. Note also that the illustrated digital signals, per the prior art, are provided at a 4× over-sampling rate, that is, they are sampled at four times the frequency of the analog input signals.
In connection with the above-described prior art implementations, note that the inclusion of each ADC comes with certain drawbacks. For example, each ADC consumes a significant amount of integrated circuit die size. As a result, device complexity and cost increase with each ADC. Indeed, in a typical video decoder, an 11-bit ADC may consume 10 percent or more in die area. As another example, note from the preceding that typically two different cores are developed for the two different geographic markets of North America and Europe, where one core includes three ADCs (for component signals) and the other includes four ADCs (for SCART). As a result, considerable research and development efforts are multiplied because they are applied differently to one core versus the other. Given these drawabacks as well as others that may be ascertained by one skilled in the art, there arises a need to address the drawbacks of the prior art, as is achieved by the preferred embodiments described below.